JETSON AGX Orin J30 GPIO EXPANSION HEADER PINOUT

Preliminary – April 7, 2022

Jetson AGX Orin Expansion Header
Sysfs GPIO Connector
Label
Pin Pin Connector
Label
Sysfs GPIO
  3.3 VDC
Power, 1A max
1
2
5.0 VDC
Power, 1A max
 
  I2C5_DAT
General I2C5 Data
I2C Bus 7
3
4
5.0 VDC
Power, 1A max
 
  I2C5_CLK
General I2C #5 Clock
I2C Bus 7
5
6
GND  
MCLK05
Audio Master Clock
7
8
UART1_TX
UART #1 Transmit
 
  GND
9
10
UART1_RX
UART #1 Receive
 
UART1_RTS
UART #1 Request to Send
11
12
I2S2_CLK
Audio I2S #2 Clock
GPIO32
GPIO #32
13
14
GND  
GPIO27

15
16
GPIO8

  3.3 VDC
Power, 1A max
17
18
GPIO35
GPIO
SPI1_MOSI
SPI #1 Master Out/Slave In
19
20
GND  
SPI1_MISO
SPI #1 Master In/Slave Out
21
22
GPIO17
GPIO
SPI1_SCK
SPI #1 Shift Clock
23
24
SPI1_CS0_N
SPI #1 Chip Select #0
  GND
25
26
SPI1_CS1_N
SPI #1 Chip Select #1
  I2C2_DAT
General I2C #2 Data
I2C Bus 1
27
28
I2C2_CLK
General I2C #2 Clock
I2C Bus 1
 
CAN0_DIN
CAN #0 Data In
29
30
GND  
CAN0_DOUT
CAN #0 Data Out
31
32
GPIO9

CAN1_DOUT
CAN #1 Data Out
33
34
GND  
I2S_FS
AUDIO I2S #2 Left/Right Clock
35
36
UART1_CTS
UART #1 Clear to Send
CAN1_DIN
CAN #1 Data In
37
38
I2S_SDIN
Audio I2S #2 Data In
  GND
39
40
I2S_SDOUT
Audio I2S #2 Data Out

Note: All signals 3.3V

Jetson AGX Orin, J30 Pin 1

Notes

I2C

Pins 3 and 5 are on I2C bus 7

For detection:

$ sudo i2cdetect -y -r 7

Pins 27 and 28 are on I2C bus 1. For detection:

$ sudo i2cdetect -y -r 1

On I2C bus 1, there are existing devices on 0x08, 0x40, 0x41. These are denoted as UU by i2cdetect

Default Setup

The initial pinmux should set all of the these pins, except for the power, UART RX TX and two I2C busses, to GPIO at boot.

Usage designations

The usages described in the above table is the official NVIDIA suggested pin usage for SFIO functionality. A modified device tree or modification to the appropriate registers is required before using as the described function.

Additional Information

Additional information for values in the table and notes are taken from Section 3.3 Expansion Header and Table 3.4. Expansion Header Pin Descriptions in the document “NVIDIA Jetson AGX Orin DevKit Carrier Board Specification” available from the NVIDIA Developer download center.

  • GPIO Max Drive or Power Pin Current Capability are available in Table 3.4. Expansion Header Pin Descriptions.
  • Pin types and direction are available in Table 3.4. Expansion Header Pin Descriptions.